vsync / atomic / config.h
Global configuration of vatomics.
The configuration defined in this file is typically applied to the whole project using vatomic.
Macros
| Macro | Description |
|---|---|
| VATOMIC_ENABLE_FENCE_RLX_NOP | maps vatomic_fence_rlx to a NOP instruction, otherwise to nothing. |
| VATOMIC_DISABLE_POLITE_AWAIT | disables polite await in x86_64 and aarch64. |
| VATOMIC_BUILTINS | uses __atomic compiler builtins to implement atomic operations. |
| VATOMIC_ENABLE_ATOMIC_SC | turns barrier mode of all atomic operations and fences to seq_cst. |
| VATOMIC_ENABLE_ATOMIC_RLX | turns barrier mode of all atomic operations and fences to relaxed. |
| VATOMIC_DISABLE_ARM64_LSE | Do not use ARM64 LSE instructions for atomic operations. |
| VATOMIC_ENABLE_ARM64_LXE | use ARM64 LSE instructions in slow path of LLSC for atomic operations. |
Macro VATOMIC_ENABLE_FENCE_RLX_NOP
maps vatomic_fence_rlx to a NOP instruction, otherwise to nothing.
Macro VATOMIC_DISABLE_POLITE_AWAIT
disables polite await in x86_64 and aarch64.
By default, vatomic_await_ functions use polite await strategies with PAUSE or WFE instructions in x86_64 and arm64, respectively. Define VATOMIC_DISABLE_POLITE_AWAIT to busy loop without such instructions.
Macro VATOMIC_BUILTINS
uses __atomic compiler builtins to implement atomic operations.
Unless VATOMIC_BUILTINS is defined, arm32 and aarch64 architectures employ custom assembly as atomics implementation. Other architectures, including x86_64, always employ compiler builtins.
Macro VATOMIC_ENABLE_ATOMIC_SC
turns barrier mode of all atomic operations and fences to seq_cst.
Macro VATOMIC_ENABLE_ATOMIC_RLX
turns barrier mode of all atomic operations and fences to relaxed.
Macro VATOMIC_DISABLE_ARM64_LSE
Do not use ARM64 LSE instructions for atomic operations.
If the compiler is configured to emit LSE instructions with some flag such as -march=armv8-a+lse, vatomic uses LSE instructions. Defining this flag disables the use of these instructions.
Macro VATOMIC_ENABLE_ARM64_LXE
use ARM64 LSE instructions in slow path of LLSC for atomic operations.
To use this option, the compiler must be configured to emit LSE instructions with some flag such as -march=armv8-a+lse.